Perceptron-Based Prefetch Filtering

Hardware prefetching is an effective technique for hiding cache miss latencies in modern processor designs. Prefetcher performance can be characterized by two main metrics that are generally at odds with one another: coverage, the fraction of baseline cache misses which the prefetcher brings into the cache; and accuracy, the fraction of prefetches which are ultimately used. An overly aggressive prefetcher may improve coverage at the cost of reduced accuracy.  Thus, performance may be harmed by this over-aggressiveness because many resources are wasted, including cache capacity and bandwidth. An ideal prefetcher would have both high coverage and accuracy.

In this talk, I will first introduce the Signature-Path Prefetcher (SPP), a simple, low-overhead, look-ahead prefetching technique, which will serve as our underlying prefetcher for the remainder of the talk. I will then introduce Perceptron-based Prefetch Filtering (PPF) as a way to increase the coverage of the underlying prefetcher without negatively impacting accuracy.  PPF enables more aggressive tuning of the underlying prefetcher, leading to increased coverage by filtering out the growing numbers of inaccurate prefetches such an aggressive tuning implies. We also explore a range of features to use to train PPF’s perceptron layer to identify inaccurate prefetches. PPF improves performance on a memory-intensive subset of the SPEC CPU 2017 benchmarks by 3.78% for a single-core configuration, and by 11.4% for a 4-core configuration, compared to the underlying prefetcher alone.



Paul V. Gratz is an Associate Professor in the department of Electrical and Computer Engineering at Texas A&M University.  His research interests include efficient and reliable design in the context of high performance computer architecture, processor memory systems and on-chip interconnection networks.  He received his B.S. and M.S. degrees in Electrical Engineering from The University of Florida in 1994 and 1997 respectively.  From 1997 to 2002 he was a design engineer with Intel Corporation.  He received his Ph.D. degree in Electrical and Computer Engineering from the University of Texas at Austin in 2008.  His paper, "Synchronized Progress in Interconnection Networks (SPIN) : A New Theory for Deadlock Freedom," was selected as a Top Pick from the architecture conferences in 2018 by IEEE Micro. His papers "Path Confidence based Lookahead Prefetching" and "B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors" were nominated for best papers at MICRO '16 and MICRO '14 respectively.  At ASPLOS '09, Dr. Gratz received a best paper award for "An Evaluation of the TRIPS Computer System."  In 2016 he received the "Distinguished Achievement Award in Teaching – College Level" from the Texas A&M Association of Former Students and in 2017 he received the "Excellence Award in Teaching, 2017" from the Texas A&M College of Engineering.


Date & time

10.30–11.30am 24 Jul 2019


Room:Seminar Room 1.33


Paul V. Gratz


6215 2394

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